Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits

This paper presents a compact multiple-valued maskprogrammable logic array (MPLA) based on a MINITSUM (MINimunl/Truncated-SU~~ two-level synthesis, A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MINplane. Since a threshold literal can be designed by using a singlejoating-gate MOS transistor, U compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding Jloating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0 .8pm CMOS design. It is demonstrated that its performance is superior to that of conventional PLA ’s.